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4A, 20ns, Dual MOSFET Drivers
IN_+
V IL
V IH
90%
MAX5055
MAX5056
V DD
OUT_
10%
MAX5057
BREAK-
P
t D-OFF1
t F
t D-ON1
t R
IN_+
BEFORE-
MAKE
CONTROL
OUT_
IN_-
V IH
t D-OFF2
V IL
t D-ON2
N
GND
RISING MISMATCH = t D-ON2 - t D-ON1
FALLING MISMATCH = t D-OFF2 - t D-OFF1
Figure 1. Timing Diagram
V DD
NONINVERTING INPUT DRIVER
MAX5055
MAX5056
V DD
MAX5054
MAX5057
BREAK-
P
IN_-
BREAK-
BEFORE-
MAKE
P
OUT_
IN_-
BEFORE-
MAKE
CONTROL
N
OUT_
CONTROL
IN_+
N
GND
INVERTING INPUT DRIVER
GND
Figure 2. MAX5054 Block Diagram (1 Driver)
Detailed Description
V DD Undervoltage Lockout (UVLO)
The MAX5054–MAX5057 have internal undervoltage
lockout for V DD . When V DD is below the UVLO thresh-
old, OUT_ is low, independent of the state of the inputs.
The undervoltage lockout is typically 3.5V with 200mV
typical hysteresis to avoid chattering. When V DD rises
above the UVLO threshold, the outputs go high or low
depending upon the logic-input levels. Bypass V DD
using low-ESR ceramic capacitors for proper operation
(see the Applications Information section).
Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams
(1 Driver)
Logic Inputs
The MAX5054B–MAX5057 have TTL-compatible logic
inputs, while the MAX5054A is a CMOS logic-input dri-
ver. The logic-input signals can be independent of the
V DD voltage. For example, the device can be powered
by a 5V supply while the logic inputs are provided from
CMOS logic. Also, the logic inputs are protected against
the voltage spikes up to 18V, regardless of the V DD volt-
age. The TTL and CMOS logic inputs have 300mV and
0.1 x V DD hysteresis, respectively, to avoid possible dou-
ble pulsing during transition. The low 2.5pF input capaci-
tance reduces loading and increases switching speed.
_______________________________________________________________________________________
9
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